1. Field of the Invention
The present invention relates to mask blanks and masks used in manufacturing semiconductor devices and display devices (display panels).
2. Description of the Related Art
For example, a photomask (reticle) used in the fine processing technology of semiconductor devices is manufactured by patterning a thin film (hereinafter referred to as a thin film, which is used for forming a mask pattern) such as a light-blocking film. The thin film is formed with the main purpose of expressing a transfer function (light-blocking, phase-shift control, transmission rate control, reflection rate control and the like) as a mask pattern formed on a transparent substrate. The patterning of the light-blocking film is performed, for example, by dry etching a resist pattern as a mask. The resist pattern is formed, for example, by electron beam lithography.
In recent years, in the mask manufacturing field, accelerating the voltage of the electron beam used in electron beam lithography to 50 keV or higher has been studied. This is because it is necessary to reduce forward scattering of the electron beam that passes through the electron beam resist and to raise the concentration of the electron beam so that a finer resist pattern can be resolved. If the accelerating voltage of the electron beam is low, the forward scattering will occur at the resist surface or in the resist; when forward scattering occurs, the resolution of the resist will deteriorate. However, if the accelerating voltage of the electron beam is 50 keV or higher, forward scattering is reduced in inverse proportion to the accelerating voltage and the energy applied to the resist is reduced by the forward scattering. Therefore, the sensitivity of the resist is insufficient and throughput ultimately drops with an electron beam resist that is used when the accelerating voltage is 10 to 20 keV, for example. Thus, in the mask manufacturing field, it has been necessary to use a chemically amplified type resist film as has been used in the fine processing technology of semiconductor wafers. Chemically amplified type resist films are highly sensitive to high-accelerating voltages and they have a high resolution (for example, see Japanese Patent Application Publication No. JP-A-2003-107675).
With a chemically amplified type resist, electron beam exposure generates acid in the chemically amplified type resist film. Using this acid as a catalyst, the acid sensitive substance reacts, changing the polymer solubility, thereby attaining either a positive type or negative type of resist.
However, when a chemically amplified type resist film is used in the mask manufacturing field, if the film density near the surface of the film (the film equivalent to the backing for the resist) directly formed by applying a chemically amplified type resist, for example, a thin film that forms a mask pattern, such as a light-blocking type film made of chrome or the like, is comparatively sparse or rough (in other words not smooth), the acid of the catalytic substance generated in the chemically amplified type resist film by electron beam exposure easily moves into the thin film (particularly in the surface layer) that forms the mask pattern that is equivalent to the backing for the resist, and movement is promoted by the acid in the film (particularly in the surface layer) that forms the mask pattern being trapped. Therefore, the concentration of acid in the bottom portion of the resist film notably drops (generally called deactivation). As a result, at an end portion of the resist pattern, the problem of “footing” occurs with the positive type chemically amplified type resist film, and the problem of “undercutting” occurs with the negative type. Conventionally, to resolve these notable shape defect problems of resist patterns caused by deactivation, a configuration has been known, in which a deactivation controlling film is disposed between a thin film that forms the mask pattern and the chemically amplified type resist film. The deactivation controlling film has a density that inhibits movement of the acid in the chemically amplified type resist film into the thin film (particularly in that surface layer) that forms the mask pattern (for example, see Japanese Patent Application Publication No. JP-A-2003-107675). The surface of the deactivation controlling film described in Japanese Patent Application Publication No. JP-A-2003-107675 is smooth compared to the thin film that forms the mask pattern whose surface is comparatively sparse or rough. It is thought that it has a surface state that does not cause “footing” or “undercutting” as a result. Japanese Patent Application Publication No. JP-A-2003-107675 discloses a configuration that introduces a material that includes Si, a silicide type material such as metal silicide, material that includes Mo, an inorganic film of a material that includes Ta, and an organic film of an organic bottom anti-reflective coating as a deactivation controlling film.
However, it was discovered that there are the following problems when the deactivation controlling film described in Japanese Patent Application Publication No. JP-A-2003-107675 is applied in a mask blank used in photolithography of a DRAM half-pitch (hp) up to 65 nm in the semiconductor design rule.
Normally, because photolithography for fine processing of semiconductor substrates is performed with reduced-size projection exposure, the size of the patterns formed on the mask for transfer are about four times the size of the patterns formed on the semiconductor substrate. However, in photolithography with a semiconductor design rule (DRAM hp up to 65 nm), because the size of circuit patterns transferred onto the semiconductor substrate have become much smaller than the wavelength of the exposure light, with reduced-size projection exposure attempting to use a transfer mask formed with a transfer pattern whose circuit pattern is expanded as it is four times, an affect such as interference of the exposure light makes it impossible to transfer the shape of the transfer pattern as it is to the resist film on the semiconductor substrate.
As super-resolution masks, an OPC mask, a phase shift mask (enhancer mask) and the like are used. The OPC mask uses the correction technology of optical proximity effects that degrades transfer characteristics by performing optical proximity effect correction (OPC). The phase shift mask (enhancer mask) uses a structure (mask enhancer) that disposes a phase shifter at a central portion of the light-blocking pattern such as a line shape so as to enhance the light-blocking characteristic of the mask pattern and improve the degree of resolution of the line pattern. For example, it is necessary to form an OPC pattern (for example an assist bar or hammer head of a line width less than 100 nm) of a size up to ½ of the circuit pattern on the OPC mask. Also, a light-blocking pattern and a phase-shifter line with extremely fine line widths are required in the enhancer mask.
Note that the enhancer mask has a distribution so that the amplitude strength of the light passed through the mask enhancer is 0 at the position that corresponds to the center of the mask enhancer, and a distribution so that the strength (the amplitude strength squared) of the light that passed through the mask enhancer is 0 at the position that corresponds to the center of the mask enhancer when the pattern width and the phase shifter width are adjusted so that the strength of the light leaking from around the edges of the light-blocking pattern to the backside of the light-blocking pattern and the strength of the light passing through the phase shifter are exactly balanced.
However, when the deactivation controlling film described in Japanese Patent Application Publication No. JP-A-2003-107675 is applied to a mask blank of a mask for transfer of the semiconductor design rule (DRAM hp up to 65 nm), although a 100 nm line and space pattern is resolved as a chemically amplified type resist pattern on a thin film that forms the mask pattern, the error of the dimension of the transfer pattern actually formed on the substrate to the design dimensions (actual dimension error) is large, and the problem occurs that the linearity up to 10 nm demanded by the above semiconductor design rule (DRAM hp up to 65 nm) cannot be secured.